1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly, to an embedded DRAM (Dynamic Random Access Memory) with an extremely large internal bus width.
2. Description of the Background Art
As microminiaturization of semiconductor memory devices continues to advance these few years, the research and development of a system LSI having a DRAM and a logic circuit both on one chip are now implemented intensively. One feature of such a DRAM/logic mounted chip is that the data transfer rate between the DRAM and the logic circuit can be improved significantly since an extremely larger internal bus width between the DRAM and the logic circuit can be implemented by usage of an interconnection layer on the chip than the case where a DRAM chip and a logic chip are mounted on a board. Here, "a large internal bus width" implies that many data can be read or written at the same time with respect to the memory cell array in the DRAM. More specifically, from the structural view of the memory cell array, many global input/output lines arranged in the memory cell array region can be activated simultaneously to transfer many data at one time through the plurality of global input/output lines.
A DRAM generally has an internal bus width of approximately 32-64 bits. Accordingly, approximately 32-64 pairs of global input/output lines are aligned. In contrast, the DRAM of a DRAM/logic mounted chip has an internal bus width of approximately 128-256 bits. It is said that the internal bus width will be increased up to approximately 1024-2048 bits in the future. Therefore, a number of global input/output lines corresponding to the increased bus width will be required.
A global input/output line is a transfer path of read/write data. In general, a write driver, a global input/output line precharge circuit, an amplifier, and the like are provided for each global input/output line.
When the internal bus width is small as in a normal DRAM, the power consumed by these circuits is small. As shown in FIG. 27, an internal power supply voltage Vcc1 is supplied to write driver 23 and global input/output line precharge circuit 24 from an internal power supply circuit 101 common to other circuitry such as a sense amplifier 25 and a peripheral circuit 90. Recent DRAMs generally include an internal power supply circuit (VDC: Voltage-Down Converter) in the chip from the standpoint of reducing power consumption and ensuring the reliability.
In an embedded memory (DRAM)/logic LSI, there is the tendency to reduce the thickness of the gate oxide film of the transistor to ensure sufficient operation speed of the transistor in the logic region. In order to use a transistor of the same size in the memory cell of a DRAM under the gate array structure, the power supply of the memory cell array, i.e., the voltage level of the power supply for operating the sense amplifier must be reduced from the standpoint of ensuring the reliability.
Reduction in the voltage level of the memory cell array power source allows power consumption to be reduced in the memory cell array. The effect of reducing the power consumption in a memory of a large capacity is great.
For the purpose of carrying out data input/output efficiently taking into account the increase in the capacity of the memory, a DRAM of a hierarchical I/O line (input/output line) structure and a DRAM directed to multi-bits are now being developed.
FIG. 28 shows an entire structure of a DRAM 500 of a hierarchical I/O line structure.
Referring to FIG. 28, DRAM 500 includes four memory mats 501, each of 16M bits, and a peripheral circuit 505.
FIG. 29 shows in detail the structure of memory mat 501. Referring to FIG. 29, memory mat 501 is further divided into subblocks 505 by a sense amplifier band 504 in which sense amplifiers are arranged and by a shunt region 502 of a word line. Each subblock 505 includes 32K memory cells connected to 256 word lines WL and 128 sense amplifiers. More specifically, memory mat 501 of 16 M bits is divided into 16 regions by sense amplifier band 504 and shunt region 502.
Column select line CSL in memory mat 501 is selected by column decoder 510 provided at the end of memory mat 501. Column select line CSL is a signal line common to the memory cells having the same column address in memory mat 501. Column select line CSL is provided common to a plurality of subblocks, extending in the column direction.
FIG. 30 shows the I/O line structure of DRAM 500. Referring to FIG. 30, DRAM 500 includes a pair of local input/output lines LIO, /LIO provided for every two sublocks 505. In response to activation of column select line CSL, the data of a selected memory cell is amplified by a sense amplifier to be transmitted to local input/output line pair LIO, /LIO. Local input/output line pair LIO, /LIO is connected to a global input/output line pair GIO, /GIO by transfer gate 520. Data is read or written through global input/output line pair GIO, /GIO via a main amplifier and a write driver 530.
FIG. 31 shows in detail a structure of transfer gate 520. Transfer gate 520 includes transistors 521 and 522 connecting local input/output line pair LIO, /LIO and global input/output line pair GIO, /GIO, and receiving a subblock select signal BS at respective gates. Transistors 521 and 522 are rendered conductive in response to activation of bank select signal BS to transmit data between local input/output line pair LIO, /LIO and global input/output line pair GIO, /GIO.
By operating memory mat 501 independently for every group of subblocks 505 by a hierarchical I/O line structure by local input/output lines and main input/output lines, data can be input/output more efficiently.
The structure of a DRAM directed to multi-bits will be described hereinafter with reference to FIG. 32.
A multi-bit DRAM 600 includes a memory mat 501 divided into a plurality of subblocks 505. DRAM 600 further includes a column decoder 510 adjacent to memory mat 501, a word line driver 550, and a main amplifier block 560. Main amplifier 560 includes a plurality of main amplifiers.
In DRAM 600, column decoder 510 is provided next to row decoder 550 arranged at the end of memory mat 501. Column select line CSL is selected by column decoder 510. Column select line CSL extends above sense amplifier band 504 provided between subblocks in a direction parallel to word line WL. A pair of main input/output lines MIO and /MIO are provided as signal lines common to subblocks 505 adjacent in the column direction, and is connected to respective main amplifiers of main amplifier band 560 at the end of memory mat 501. A data read/write operation is carried out through main input/output line pair MIO, /MIO via a main amplifier.
FIG. 33 shows in detail the structure of DRAM 600. In subblock 505, the main input/output line pair includes, for example, 128 input/output line pairs MIO1, /MIO1-MIO128, /MIO128. According to this structure, each of main input/output line pairs MIO1, /MIO1-MIO128, /MIO128 is provided for every 4 pairs of bit lines BL and /BL in subblock 505. Each bit line pair B1, /BL is connected to sense amplifiers SA1-SA512, respectively, in sense amplifier band 504. Sense amplifiers SA1-SA512 amplify the data stored in the memory cell transmitted through bit line pair BL, /BL, and are connected to main input/output line pairs MIO1, /MIO-MIO128, /MIO128 via transmission gate pairs N1-N512. Transmission gates N1-N512 include an N type transistor having its gate connected to column select line CSL to connect a sense amplifier with a main input/output line pair.
In response to activation of column select line CSL, the 128 pairs of transmission gates are rendered conductive, whereby 128 bits of data can be input/output by one column select operation through main input/output line pairs MIO1, /MIO1-MIO128, MIO128.
Thus, the number of processed data per one column select operation can be increased in multi-bit DRAM 600 than for a conventional DRAM.
When there are a great number of global input/output lines as in the case of an embedded DRAM/logic LSI chip, the power consumed by write driver 23 and global input/output line precharge circuit 24 is particularly increased. This is because the power is consumed in the charge/discharge operation of the global input/output line in write driver 23 and in the precharge operation of the global input/output line in global input/output line precharge circuit 24. Therefore, when an internal power supply circuit common to other circuits such as sense amplifier 25 and peripheral circuit 90 is used for write driver 23 and global input/output line precharge circuit 24 as shown in FIGS. 20 and 21, the internal power supply voltage is reduced by the great current consumed in the operation of write driver 23 and global input/output line precharge circuit 24 to induce bouncing. This becomes the cause of erroneous operation of other circuits.
As mentioned above, the voltage level of power supply for the memory cell array must be reduced particularly in the above-described embedded DRAMs. If the voltage level of the power supply for the write driver that writes externally applied data is set equal to the power supply voltage level that drives the peripheral circuits such as a logic circuit and the like as in the conventional case, the following problem will be encountered.
The level of the power supply voltage of a write driver corresponds to the amplitude level of an I/O line. A great amplitude level of an I/O line implies that the time required for the equalize operation of an I/O line carried out prior to a data write/read operation becomes longer. Particularly for a data readout operation following a data write operation, the operation speed is rate-determined by the time of the equalize operation. This problem will become a bottleneck in increasing the operation speed of the DRAM.
In the above-described embedded DRAM, the number of data that can be processed at one time, i.e., the number of I/O lines rendered active, is significantly great since the data bus has a large width. The amplitude level of an I/O line greatly affects the power consumption of the entire DRAM.
If the voltage level of the memory cell array power supply is reduced, it will become difficult to form the transfer gate employed in the application of the hierarchical I/O line system in a DRAM only by the N type transistor as shown in FIG. 31. In accordance with reduction in the voltage level of the sense amplifier power supply, the voltage level corresponding to an H level of data becomes lower. Sufficient voltage level cannot be obtained in writing data of an H level with the transfer gate formed by only an N type transistor due to the drop of the threshold voltage of the N type transistor.